bi-cmos & dmos 32bit serial-input latched driver m 566 92 f p mitsubishi des cri pt i o n the M56692FP is a semiconductor integrated circuit that has a built-in, 32-bit shift register and a latch of cmos structure with serial input and serial/parallel output, and a 32-bit totem-pole-type parallel output driver o f high pressure proof dmos structure. employed are bi-cmos and high pressure proof dmos processing technology. f e at ures l serial input - serial/parallel output l bidirectional shift register (controlled at f/r terminal) l cascade connections possible through serial output. l latch circuit included for each stage. l driver supply voltage: v h =90v l operating temperature: -40 ? 85 c app l i cat i o n vacuum fluorescent display grid driver pi n c o n f i g urat i o n ( t o p v i e w) 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 v h sout(sin) v dd f/r lgnd clk lat sin(sout) v h blk pgnd hvo 1 hvo 2 hvo 3 hvo 4 hvo 5 hvo 6 hvo 7 hvo 8 hvo 9 hvo 10 hvo 11 hvo 22 hvo 21 hvo 20 hvo 19 hvo 18 hvo 17 hvo 16 hvo 15 hvo 14 hvo 13 hvo 12 34 35 36 37 38 39 40 41 42 43 44 pgnd hvo 32 hvo 31 hvo 30 hvo 29 hvo 28 hvo 27 hvo 26 hvo 25 hvo 24 hvo 23 outline 44p6n-a m5 6692 fp 3-58 b l oc k d ia gr a m hvo 32 hvo 31 hvo 30 hvo 3 hvo 2 hvo 1 pgnd sout (sin) output protect circuit 8 7 9 6 q t d q l d q t d q l d q t d q l d q t d q l d q t d q l d q t d q l d 2 42 43 41 14 13 12 bl k lat sin (sout) clk 44 v h v dd lgnd 10 11 1 3 5 4 f/r
bi-cmos & dmos 32bit serial-input latched driver m 566 92 f p mitsubishi hvo1?2 output driver (push-pull) function pin name pi n f unct i o n d escri p t i o n v dd lgnd v h pgnd clk sin sout lat blk f/r serial data output latch input. when the latch is set to ?? the data in the shift resister will enter the each latch circuit. when the latch input is set to ?? the data will be held. enable input for output control. when the blk input is set to ?? data in the latch circuit will appear at outputs. when the blk input is set to ?? all outputs will be set to ?? direction control for the internal shift resister logic stage supply voltage logic stage ground output stage supply voltage output stage supply ground clock input for the internal shift resister. the data enter the internal shift resisters and the data in the shift registers wi ll be shifted in order by high to low change of the clock. serial data input logic inputs voltage output voltage power dissipation range storage temperature range logic output voltage logic stage supply voltage output stage supply volta ge vi v hv o tstg -0.3 ? 90 v o -0.3 ? v dd +0.3 v dd -0.3 ? 7 v h pd -0.3 ? v dd +0.3 -0.3 ? v h -55 ? 150 850 high supply voltage output pin symbol ratings unit parameter conditions abs o l ut e m axi m um rat i ng s (ta=25 c, unless otherwise noted) v v v v v c mw ta 25 c data output tr ut h t able 2. l a tch a n d d r iv er sect ion s hvon dn lat blk x h l x dn=nth bit dff retention data hvon=nth bit driver output l = ?? level h = ?? level x = ?? level or ??level tr ut h t able 1. s h if t r egi s ter s e c tio n clk h or l shift register data is shifted. no changes. t rut h t abl e x h h l h l l l output all ? h l latch? data output. h or l f/r h h l l input input/output sin(sout) in in out out sout(sin) out out in in data is shifted. no changes. serial-output sout i s used b y connecting t o the next stage M56692FP sin when more than one M56692FP is used to expand bits in the series. in accordance with truth table 2, parallel output allows the latch to pass data through if lat input is turned to ?? and data to b e retained if lat input is turned to ?? driver output hvon allows data from the latch to be output if blk input is turned to ?? and ? to be output if blk input is turned to ?? irrespective of data from the latch. f unct i o n the M56692FP comprises a 32 bit bidirectional shift register, a 32 bit latch, and a parallel output hvo 1 ?hvo32 connected to i t s output. in accordance with truth table 1, the data transfer direction of shift register depends upon f/r input, and f/r being at ??or open allows pin 9 to turn to sin and pin 2 to turn to sout, and f / r being at ?? allows pin 2 to turn to sin and pin 9 to turn to sout, permitting data transfer from sin to sout, respectively. inputting data to sin and clock pulse to clk allows sin signal t o be put into the internal shift register when the clock changes from ?? to ?? and shift register data to be shifted sequentially.
bi-cmos & dmos 32bit serial-input latched driver m 566 92 f p mitsubishi ro = 220k w co = 50pf driver output propagation time t plh(so) logic output propagation time v -1 -500 sin, lat, clk blk, f/r v th v tl output protect operating voltage i hvoh ??output current v oh v ol logic output voltage v hvoh driver output voltage v hvol i h supply current 2 1 bit ?? no load operating temperature supply voltage supply voltage topr 40 ? 90 v dd 4 ?6 v h -40 ? 85 symbol ratings unit parameter conditions rec o m m e nde d o perat i n g c o ndi t i o n s v v c limits min. typ. max. symbol test conditions unit parameter el ect r i cal charact eri s t i cs (v dd =5v, v h =80v and t a =25 c, unless otherwise noted) i dd i hvol supply current 1 ??input current ??output current i oh = -0.1ma 70 4.5 0.4 0 0.4 0 -250 75.5 4.9 3.3 3.0 2 1 1 2.5 ma ma ma v v i ih i il ??input current no load output all ?? no load i hvoh = -50ma i hvol = 10ma v ih =5v input pin i ol = 0.1ma v il = 0v 01 m a 0.5 0.1 -50 10 0.4 m a m a v ma ma limits min. typ. max. symbol test conditions unit parameter sw i t chi ng chara ct e r i s t i cs (v dd =5v, v h =80v and ta=25 c, unless otherwise noted) fclk t phl(so) tp h l ( o u t ) trout tfout clock frequency driver output rise and fall time duty = 45 ? 55% 90 60 70 35 65 8 180 180 mhz ns ns ns tp l h ( o u t ) cl = 15pf 95 ns ns ns t est ci rcui t pg dut cl co 50 w sout hvon v h v dd input ro (1) characteristics of pulse generator (pg) tr 20ns tf 20ns (2) capacitance cl includes connection floating capacitance and probe input capacitance. : ro=220k w : co=50pf duty cycle 2.5%* -100 20 * maximum numbers of outputs high state are two at the same time.
bi-cmos & dmos 32bit serial-input latched driver m 566 92 f p mitsubishi t i m i ng wav e f o rm sout hvon sin blk clk 1/fmax th tsu tfso trso tr out tf out t plh(out) 50% 50% 50% 50% 50% 50% t phl(so) 50% 50% 50% t phl(out) 90% 10% 90% 50% 10% t plh(so) 90% 10% 90% 10% 50%
bi-cmos & dmos 32bit serial-input latched driver m 566 92 f p mitsubishi (note) duty cycle vs permissible output current 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 output current i oh (ma) duty cycle (%) 0 10 20 30 40 50 60 70 80 90 100 0 2 04 0 6 08 0 1 0 0 duty cycle vs permissible output current note 1 2 4 8 16 24 32 1 2 4 8 16 24 32 duty cycle (%) t ypi cal charac t e r i s t i c s power dissipation pd(w) 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 thermal derating t emperature ta ( c) driver output v on ? oh -100 -80 -60 -40 -20 0 0 2 468 1 0 ta=25 c ??output on voltage v on (v) ??output current i oh (ma) 12 ta=-40 c ta=85 c output current i oh (ma) 1. v dd =5v and v h =80v unless otherwise noted. 2. thermal derating curve represents that of an individual ic unit. 3. allowable duty cycle output curve represents that when a standard substrate is mounted. (standard substrate: 70x70x1.6mm glass epoxy) ta=25 c repeated frequency>100hz figure i n the circle represents the number o f concurrently operating output circuits. current value denotes a numerical value per circuit. note ta=85 c repeated frequency>100hz figure i n the circle represents the number o f concurrently operating circuits. current value denotes a numerical value per circuit.
|
